The present invention relates to network processor devices, and particularly, a system and method for simplifying the design of complex System-on-Chip (SOC) implementations by providing a self-contained processor subsystem as a component for System-on-Chip design.
Current state-of-the-art of building SoCs requires the designer to, inter alia: a) assemble from basic components such as microprocessors, memories, basic I/O macros (e.g., a framer); b) model bus-contention between the different devices, and select appropriate bus structures; c) integrate all components during SoC hardware design; and d) integrate all components using custom software.
However, there are inherent problems with the state-of-the art SoC design methodologies, including, but not limited to: it is labor-intensive; it is error-prone; it requires highly-skilled designers familiar with a particular application domain; it demands high modeling overhead for bus modeling and/or contention on a common system bus; it requires hardware and software integration to provide such basic services as TCP/IP, InfiniBand, FibreChannel, iSCSI and other standardized protocols. An example of a successful SoC integration design approach has been implemented in the MPC8560 Integrated Communications Processor available from Motorola, Inc.
Other approaches to SoC design where multiple subsystems are integrated on a card or board exhibit problems due to component count which drives system cost, increased failure susceptibility, and the cost of high-interconnect multi-layer boards.
FIGS. 1 and 2 illustrate respective prior art implementations of a Network Processor chip 10 (FIG. 1) and 15 (FIG. 2) each including multiple processing cores 20, local memory, data memory, link memory, CPU, buffers, and PHY (network physical layer) interfaces. These are stand-alone NPU's (Network Processor Units) that do not connect to an “open” system bus via a common macro.
FIG. 3 illustrates a prior art implementation of a Network Processor chip 30 including processors 40, a system bus, cache, and local memory connected through a “bridge” such as the PCI (Peripheral Components Interconnection bus) bridge to a local processor bus commonly used in today's systems.
It would thus be highly desirable to provide an SoC integrated circuit having a multiprocessor subsystem as component and further a self-contained multiprocessor subsystem having predefined functionality for implementation as an independent SoC component and further, provides multithreading capability.
Relevant references describing aspects of SoC processor and component design include:
U.S. Pat. No. 6,331,977 describes a System on a chip (SOC) that contains a crossbar switch between several functional I/Os internal to the chip and number of external connection pins, where the number of pins is less than the number of internal I/Os.
U.S. Pat. No. 6,262,594 describes an apparatus and method implementing a crossbar switch for configurable use of group of pads of a system on chip.
U.S. Pat. No. 6,038,630 describes an apparatus and method implementing a crossbar switch for providing shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses.
U.S. Patent application No. US2002/0184419 describes an ASIC which enables use of different components for a system on a chip using a common bus system and describes wrappers for functional units with different speed and data width to achieve compatibility with a common bus.
U.S. Patent application No. US2002/0176402 describes an octagonal interconnection network for linking functional units on a SoC. The functional units on the interconnection network are organized as a ring and use several crossing data links coupling halfway components.
U.S. Patent application No. US2001/0042147 describes a system resource router for SOC interconnection, comprising two channel sockets with connect each data cache (D-cache) and instruction (I-cache). Also included are external data transfer initiators, two internal M-channel buses, and an M-channel controller to provide the interconnection.
U.S. Patent application No. US2002/0172197 describes a communication system connecting multiple transmitting and receiving devices via a crossbar switch embedded on a chip in a point-to-point fashion.
U.S. Patent application No. US2001/0047465 describes several variations of an invention providing a scalable architecture for a communication system (typically a SOC or ASIC) for minimizing total gates by dividing transmissions into individual transmission tasks, determining a computational complexity for each transmission task and computational complexity being based on the number of MIPS per circuit.
In the reference entitled “On-Chip Interconnects for Next Generation System-on-Chips” by A. Brinkmann, J. C. Niemann, I. Hehemann, D. Langen, M. Porrmann, and U. Ruckert, Conf. Proceedings of ASIC2003, Sep. 26–27, 2003, Rochester, N.Y., there is described an SoC architecture utilizing active switch boxes to connect processor cells for enabling packet network communications. This paper makes no mention or description of a processor core with multi-threading capability.
In the reference entitled “A Comparison of Five Different Multiprocessor SoC Bus Architectures” by Kyeong Keol Ryu, Eung Shin, and Vincent J. Mooney, Conf. proceedings of Euromicro Symposium on Digital System Design (DSS'01), Sep. 04–06, 2001, Warsaw, Poland, there is described Multiprocessor SoC bus architectures including Global Bus I Architecture (GBIA), Global Bus II Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and CoreConnect Bus Architecture (CCBA).
None of the prior art configurations teach a processor core that comprises multiple sub-processors (thread groups) each with locally connecting SRAM or eDRAM in a multithreading configuration in order to improve processor performance and further SOC, ASIC, NP, or DSP integration.